Institution · Cadence Design Systems (India)
Most cited papers from Cadence Design Systems (India)
What are the most cited papers from Cadence Design Systems (India)?
The most cited paper from Cadence Design Systems (India) is "Vector space theoretic analysis of additive cellular automata and its application for pseudoexhaustive test pattern generation" (Aloke Kumar Das, P.P. Chaudhuri, 1993), with 94 citations. Next come "Post-placement voltage island generation under performance requirement" (46) and "Virtual platforms: Breaking new grounds" (41).
Showing 50 of 62 papers. Every paper with more than 3 citations is listed.
| # | Paper | ||
|---|---|---|---|
| 1 | Vector space theoretic analysis of additive cellular automata and its application for pseudoexhaustive test pattern generation Aloke Kumar Das, P.P. Chaudhuri · IEEE Transactions on Computers | Mar 1993 | 94 |
| 2 | Post-placement voltage island generation under performance requirement Huaizhi Wu, I-Min Liu, Martin D. F. Wong et al. | 22 Dec 2005 | 46 |
| 3 | Virtual platforms: Breaking new grounds Rainer Leupers, Frank Schirrmeister, Grant Martin et al. | Mar 2012 | 41 |
| 4 | DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks Sergej Deutsch, Brion Keller, Vivek Chickermane et al. | Nov 2012 | 38 |
| 5 | Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study Sandeep Goel, Saman Adham, Min-Jer Wang et al. | Sep 2013 | 38 |
| 6 | Formal verification of an ARM processor Vinayak Patankar, Alok Kumar Jain, Randal E. Bryant | 1999 | 36 |
| 7 | A Study on COVID–19, Its Origin, Phenomenon, Variants, and IoT-Based Framework to Detect the Presence of Coronavirus Vikas Menon, Digvijay Pandey, Dishant Khosla et al. · EAI/Springer Innovations in Communication and Computing | 30 Sep 2022 | 31 |
| 8 | Memristor based high linear range differential pair David Varghese, Gaurav Gandhi | Jul 2009 | 29 |
| 9 | CIRCUIT MIMICKING TiO2 MEMRISTOR: A PLUG AND PLAY KIT TO UNDERSTAND THE FOURTH PASSIVE ELEMENT Avantika Sodhi, Gaurav Gandhi · International Journal of Bifurcation and Chaos | Aug 2010 | 27 |
| 10 | Automation of 3D-DfT Insertion Sergej Deutsch, Vivek Chickermane, Brion Keller et al. | Nov 2011 | 22 |
| 11 | Dopingless 1T DRAM: Proposal, Design, and Analysis A Harrington James, Sneh Saurabh · IEEE Access | 2019 | 20 |
| 12 | A general graph theoretic framework for multi-layer channel routing Rajat Kumar Pal, Alak Kumar Datta, Sujata Pal et al. | 19 Nov 2002 | 19 |
| 13 | A Pseudo Cross-Coupled Switch-Capacitor Based DC-DC Boost Converter for High Efficiency and High Power Density Tamal Das, Sankalan Prasad, Samiran Dam et al. · IEEE Transactions on Power Electronics | 31 Jan 2014 | 19 |
| 14 | SmartScan - Hierarchical test compression for pin-limited low power designs Krishna Chakravadhanula, Vivek Chickermane, D. Pearl et al. | Sep 2013 | 19 |
| 15 | Neuromorphic Accelerator for Spiking Neural Network Using SOT-MRAM Crossbar Array Gaurav Verma, Arshid Nisar, Seema Dhull et al. · IEEE Transactions on Electron Devices | 4 Oct 2023 | 18 |
| 16 | Ethernet based smart energy meter for power quality monitoring and enhancement Himshekhar Das, Lalit Chandra Saikia | Oct 2017 | 15 |
| 17 | A 0.29pJ/b 5.27Tb/s/mm UCIe Advanced Package Link in 3nm FinFET with 2.5D CoWoS Packaging Didem Turker Melek et al. | 16 Feb 2025 | 12 |
| 18 | High throughput multiple device diagnosis system Sameer Chillarige, Anil K. Malik, Sharjinder Singh et al. | Oct 2017 | 12 |
| 19 | Design and Comparative Analysis of Heterogeneous Gate Dielectric Nanosheet TFET with Temperature Variance Garima Jain, Ravinder Singh Sawhney, R. Deepak Suresh Kumar et al. · Silicon | 14 Jul 2022 | 11 |
| 20 | Evaluating BIST architectures for low power C.P. Ravikumar, N Prasad | 27 Nov 2002 | 11 |
| 21 | Improved First-Order Parameterized Statistical Timing Analysis for Handling Slew and Capacitance Variation Ratnakar Goyal, Sachin Kumar Shrivastava, Harindranath Parameswaran et al. | 2007 | 11 |
| 22 | A new algorithm for implementation of design functions by available devices R.S. Mitra, Partha S. Roop, A. Basu · IEEE Transactions on Very Large Scale Integration (VLSI) Systems | Jun 1996 | 11 |
| 23 | Modeling the effectiveness of decoupling capacitors for multilayer PCBs Bruce R. Archambeault, P. Wetmore, Xingchao Chuck Yuan et al. | 27 Nov 2002 | 11 |
| 24 | Stability of states in a squeezed environment Kanwarpreet S. Grewal · Physical Review A | 13 Feb 2003 | 10 |
| 25 | Accurate computation of field reject ratio based on fault latency Dulal Chandra Das, Sharad C. Seth, Vishwani D. Agrawal · IEEE Transactions on Very Large Scale Integration (VLSI) Systems | Dec 1993 | 9 |
| 26 | Tabu search based behavioural synthesis of low leakage datapaths Chandramouli Gopalakrishnan, Srinivas Katkoori · IEEE Computer Society Annual Symposium on VLSI | 4 Oct 2004 | 9 |
| 27 | Parallel Algorithm for Shortest Pairs of Edge-Disjoint Paths Santo Banerjee, R. K. Ghosh, A. Phani Kumar Reddy · Journal of Parallel and Distributed Computing | Mar 1996 | 9 |
| 28 | 2 GHz low power double edge triggered flip-flop in 65nm CMOS technology Imran Ahmed Khan, Danish Shaikh, Mirza Tariq Beg | Mar 2012 | 9 |
| 29 | Extended Hamiltonian Pencil for passivity assessment and enforcement for S-parameter systems Zuochang Ye, Luis Miguel Silveira, Joel R. Phillips | Mar 2010 | 8 |
| 30 | A multiplier generator for Xilinx FPGAs Jaikaran Singh, Anshul Kumar, Suthikshn Kumar | 23 Dec 2002 | 8 |
| 31 | Low-Power Design Using the Si2 Common Power Format Susan Carver, Anmol Mathur, Lalit Kumar Sharma et al. · IEEE Design & Test of Computers | 10 Jan 2012 | 8 |
| 32 | Heuristic search based approach to scheduling, allocation and binding in Data Path Synthesis Alok Kumar, Alok Kumar, S. Balakrishnan | 19 Nov 2002 | 7 |
| 33 | Scalable parallel event-driven HDL simulation for multi-cores Tariq Bashir Ahmad, Namdo Kim, Byeong Min et al. | Sep 2012 | 7 |
| 34 | Design of the 3.7 GHz, 1 kW CW solid state driver for LHCD system of the SST-1 tokamak Sandeep R. Sainkar, Alice N. Cheeran, M. Janga Reddy et al. · Fusion Engineering and Design | 6 May 2020 | 6 |
| 35 | Leakage Power Driven Behavioral Synthesis of Pipelined Datapaths R. Gopalan, Chandramouli Gopalakrishnan, Srinivas Katkoori | 24 May 2005 | 6 |
| 36 | Spin device-based image edge detection architecture for neuromorphic computing Gaurav Verma, Sandeep Soni, Brajesh Kumar Kaushik · Nanotechnology | 5 Oct 2023 | 5 |
| 37 | An Efficient Method For Generic Dsp Implementation Of Dilated Convolution Harinarayanan. E. V, Sachin Ghanekar · ICASSP 2022 - 2022 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP) | 27 Apr 2022 | 5 |
| 38 | An 8-Channel Varactor-Less 28-GHz Front End With 7-Bit Resolution 340° RTPS for 5G RF Beamformers Ritabrata Bhattacharya, Vikas Aggarwal, Ashish Gupta et al. · IEEE Transactions on Circuits & Systems II Express Briefs | 25 Oct 2019 | 5 |
| 39 | A 28GHz, 7mW, 32dB Gain and 3.3dB NF, Gm-Boosted CG-CS LNA for 5G RF Beamformers Ritabrata Bhattacharya, Vikas Aggarwal, Ashish Gupta et al. | May 2019 | 5 |
| 40 | Improving Diagnosis Resolution and Performance at High Compression Ratios Sameer Chillarige, Atul K. K. Chhabra, Anil K. Malik et al. | Oct 2018 | 5 |
| 41 | Design and comparative analysis of low power 64 Bit SRAM and its peripherals using power reduction techniques Gaurav Vashisht, Hitesh Pahuja, B. P. Singh et al. | Oct 2016 | 5 |
| 42 | Timing skew enabler induced by fiber weave effect in high speed HDMI channel by angle routing technique in 3DFEM Surender Singh, Taranjit Kukal | Oct 2015 | 5 |
| 43 | VLSI implementation of a wormhole router using virtual channels Abhishant Prakash, C.P. Ravikumar | 17 Dec 2002 | 5 |
| 44 | Improved Timing Windows Overlap Check Using Statistical Timing Analysis Smriti Shrivastava, Harindranath Parameswaran | 2011 | 5 |
| 45 | A 0.52pJ/bit 0.448Tbps/mm UCIe Standard Package Die-to-Die Transceiver with Low-Latency TX Clock Alignment in 3nm FinFET James Vandersand, Didem Turker Melek, Kevin Geary et al. | 8 Jun 2025 | 4 |
| 46 | On Outage Performance and Ergodic Capacity Analysis of Two User NOMA in a Cooperative Cognitive Radio Network With an Energy Harvesting Relay Alok Kumar Baranwal, Hritwika Sarkar, Shashibhushan Sharma et al. · International Journal of Communication Systems | 24 Feb 2025 | 4 |
| 47 | Substantial Capabilities of 3-Axis Robotic Arm in Industry Automation Applications Gaurav Sharma, A. Sri Ganesh, Sandeep Kumar et al. | 8 Sep 2023 | 4 |
| 48 | Implementation of Self-Controlled Wheelchairs based on Joystick, Gesture Motion and Voice Recognition Renu Kumawat, Aman Dayal, Seshadhari Srinivasan · 2021 IEEE International Symposium on Smart Electronic Systems (iSES) | Dec 2021 | 4 |
| 49 | Core Test Language based High Quality Memory Testing and Repair Methodology Puneet Arora, Patrick L. Gallagher, Steven L. Gregor | 18 Jul 2021 | 4 |
| 50 | Comparison of Millimeter Wave Quadrature-VCOs for 28GHz 5G Applications Vikas Aggarwal, Ritabrata Bhattacharya, Taranjit Kukal et al. | 29 Sep 2020 | 4 |
Citations are OpenAlex's own counts, from its 2026-09-23 snapshot, so the ranking can differ from Google Scholar or Web of Science. A paper is listed for an institution when any of its authors gave it as an affiliation; retracted papers and papers whose citation count cannot be traced to citing works are left out, and a preprint and the article it became are shown once. Release dates are OpenAlex's: where a source gave only a month or a year, that is what is shown. How the lists are chosen.