Institution · Cirrus Logic (United States)
Most cited papers from Cirrus Logic (United States)
What are the most cited papers from Cirrus Logic (United States)?
The most cited paper from Cirrus Logic (United States) is "Signal processing applications of oblique projection operators" (R.T. Behrens, Louis L. Scharf, 1994), with 473 citations. Next come "Testing embedded-core based system chips" (427) and "NULL Convention Logic/sup TM/: a complete and consistent logic for asynchronous digital circuit synthesis" (318).
Showing 50 of 59 papers. Every paper with more than 45 citations is listed.
| # | Paper | ||
|---|---|---|---|
| 1 | Signal processing applications of oblique projection operators R.T. Behrens, Louis L. Scharf · IEEE Transactions on Signal Processing | Jun 1994 | 473 |
| 2 | Testing embedded-core based system chips Y. Zorian, Erik Jan Marinissen, S. Dey | 27 Nov 2002 | 427 |
| 3 | NULL Convention Logic/sup TM/: a complete and consistent logic for asynchronous digital circuit synthesis Karl M. Fant, Scott Brandt | 23 Dec 2002 | 318 |
| 4 | The Nightsat mission concept Christopher D. Elvidge, Pierantonio Cinzano, D. R. Pettit et al. · International Journal of Remote Sensing | 29 May 2007 | 296 |
| 5 | 2001 technology roadmap for semiconductors AJ Allan, D. Edenfeld, William H. Joyner et al. · Computer | 2002 | 260 |
| 6 | Towards a standard for embedded core test: an example Erik Jan Marinissen, Y. Zorian, R. Kapur et al. | 20 Jan 2003 | 162 |
| 7 | Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!) Charles E. Stroud, S. Konala, Ping Chen et al. | 23 Dec 2002 | 161 |
| 8 | Asynchronous design using commercial HDL synthesis tools M. Ligthart, Karl M. Fant, R. Lowell Smith et al. | 7 Nov 2002 | 157 |
| 9 | A simplified polynomial-fitting algorithm for DAC and ADC BIST Stephen Sunter, Naveena Nagi | 23 Nov 2002 | 155 |
| 10 | An approach to systems verification William R. Bevier, Warren A. Hunt, J Strother Moore et al. · Journal of Automated Reasoning | Dec 1989 | 145 |
| 11 | Microprocessor design verification Warren A. Hunt · Journal of Automated Reasoning | Dec 1989 | 132 |
| 12 | CMOS circuit design of threshold gates with hysteresis Gerald E. Sobelman, Karl M. Fant | 27 Nov 2002 | 126 |
| 13 | Learning From Crisis Sharon S. Dawes, Anthony M. Cresswell, Bruce B. Cahan · Social Science Computer Review | Feb 2004 | 125 |
| 14 | Compensation of Frequency-Dependent Gain/Phase Imbalance in Predistortion Linearization Systems Lei Ding, Zhengxiang Ma, Dennis R. Morgan et al. · IEEE Transactions on Circuits and Systems I Regular Papers | Feb 2008 | 120 |
| 15 | Test of RAM-based FPGA: methodology and application to the interconnect M. Renovell, Joan Figueras, Y. Zorian | 22 Nov 2002 | 115 |
| 16 | A mechanically verified language implementation J Strother Moore · Journal of Automated Reasoning | Dec 1989 | 110 |
| 17 | Low-Area/Power Parallel FIR Digital Filter Implementations David A. Parker, Keshab K. Parhi · The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology | Sep 1997 | 106 |
| 18 | Kit: a study in operating system verification William R. Bevier · IEEE Transactions on Software Engineering | 1989 | 103 |
| 19 | Robust Detection of Audio-Cough Events Using Local Hu Moments Jesús Monge-Álvarez, Carlos Hoyos-Barceló, Paul Lesso et al. · IEEE Journal of Biomedical and Health Informatics | Feb 2018 | 99 |
| 20 | Integer programming based topology selection of cell-level analog circuits P.C. Maulik, Larry Richard Carley, Rob A. Rutenbar · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | Apr 1995 | 99 |
| 21 | Optimization of NULL convention self-timed circuits Scott C. Smith, Ronald F. DeMara, Jiann Shiun Yuan et al. · Integration | 8 Jan 2004 | 98 |
| 22 | A 1.5 mW 68 dB SNDR 80 Ms/s 2 $\times$ Interleaved Pipelined SAR ADC in 28 nm CMOS Frank van der Goes, Christopher M. Ward, Santosh Astgimath et al. · IEEE Journal of Solid-State Circuits | 23 Oct 2014 | 97 |
| 23 | The Boyer-Moore theorem prover and its interactive enhancement R. S. Boyer, Matt Kaufmann, J Strother Moore · Computers & Mathematics with Applications | 1995 | 97 |
| 24 | Test metrics for analog parametric faults Stephen Sunter, Naveena Nagi | 20 Jan 2003 | 97 |
| 25 | Estimators of the Magnitude-Squared Spectrum and Methods for Incorporating SNR Uncertainty Yang Lu, Philipos C. Loizou · IEEE Transactions on Audio Speech and Language Processing | Oct 2010 | 95 |
| 26 | Digital-compatible high-performance operational amplifier with rail-to-rail input and output ranges Wen-Chi Wu, W.J. Helms, Jutta Kühn et al. · IEEE Journal of Solid-State Circuits | 1994 | 92 |
| 27 | Potential for global mapping of development via a nightsat mission Christopher D. Elvidge, Jeffrey Safran, Benjamin T. Tuttle et al. · GeoJournal | 19 Sep 2007 | 89 |
| 28 | A 9-bit, 14 μW and 0.06 mm$^{2}$ Pulse Position Modulation ADC in 90 nm Digital CMOS Shahrzad Naraghi, M. Courcy, Michael P. Flynn · IEEE Journal of Solid-State Circuits | 24 Aug 2010 | 87 |
| 29 | A least-squares/Newton method for digital predistortion of wideband signals Lei Ding, Zhengxiang Ma, Dennis R. Morgan et al. · IEEE Transactions on Communications | May 2006 | 85 |
| 30 | A mechanically verified code generator WilliamD. Young · Journal of Automated Reasoning | Dec 1989 | 78 |
| 31 | On-chip digital jitter measurement, from megahertz to gigahertz Stephen Sunter, Aubin Roy · IEEE Design & Test of Computers | Jul 2004 | 77 |
| 32 | The IMMULITE assay tube: a new approach to heterogeneous ligand assay Arthur L. Babson, Dan Olson, T Palmieri et al. · Clinical Chemistry | Sep 1991 | 77 |
| 33 | A parallel improvement algorithm for the bipartite subgraph problem K.C. Lee, Nobuo Funabiki, Yoshiyasu Takefuji · IEEE Transactions on Neural Networks | 1992 | 76 |
| 34 | Symbolic analysis of bounded Petri nets Enric Pastor, Jordi Cortadella, Oriol Roig · IEEE Transactions on Computers | May 2001 | 75 |
| 35 | An artificial maximum neural network: a winner-take-all neuron model forcing the state of the system in a solution domain Yoshiyasu Takefuji, Kuo-Chun Lee, Hideo Also · Biological Cybernetics | Jul 1992 | 74 |
| 36 | On the baseband representation of a bandpass nonlinearity G. Tong Zhou, Hua Lin Qian, Lei Ding et al. · IEEE Transactions on Signal Processing | 19 Jul 2005 | 74 |
| 37 | Task generation and compile-time scheduling for mixed data-control embedded software Jordi Cortadella, Alex Kondratyev, Luciano Lavagno et al. | 2000 | 74 |
| 38 | A 114-db 68-mW chopper-stabilized stereo multibit audio ADC in 5.62 mm/sup 2/ Yuqing Yang, A. Chokhawala, M. Alexander et al. · IEEE Journal of Solid-State Circuits | Dec 2003 | 74 |
| 39 | Delay-insensitive gate-level pipelining Scott C. Smith, Ronald F. DeMara, Jiann Shiun Yuan et al. · Integration | Oct 2001 | 70 |
| 40 | A 10-bit 50 MS/s Pipelined ADC With Capacitor-Sharing and Variable-$g_{m}$ Opamp Byung‐Geun Lee, Robin M. Tsang · IEEE Journal of Solid-State Circuits | 26 Feb 2009 | 63 |
| 41 | Riffle shuffles, cycles, and descents Persi W. Diaconis, Michael Mc Grath, Jim Pitman · COMBINATORICA | Mar 1995 | 61 |
| 42 | An 8/9 rate time-varying trellis code for high density magnetic recording W.G. Bliss · IEEE Transactions on Magnetics | 1997 | 60 |
| 43 | Trace table based approach for pipelined microprocessor verification Jun Sawada, Warren A. Hunt · Lecture notes in computer science | 1997 | 60 |
| 44 | A digital read/write channel with EEPR4 detection D.R. Welland, S. Phillip, Ka Leung et al. | 17 Dec 2002 | 57 |
| 45 | Single-Chain HLA-A2 MHC Trimers That Incorporate an Immundominant Peptide Elicit Protective T Cell Immunity against Lethal West Nile Virus Infection Sojung Kim, Lijin Li, Curtis McMurtrey et al. · The Journal of Immunology | 9 Mar 2010 | 55 |
| 46 | Analog VLSI implementations of auditory wavelet transforms using switched-capacitor circuits Jyhfong Lin, Wing‐Hung Ki, Thomas G. Edwards et al. · IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications | 1994 | 55 |
| 47 | Switching activity generation with automated BIST synthesis for performance testing of interconnects Rajesh Pendurkar, Abhijit Chatterjee, Y. Zorian · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2001 | 54 |
| 48 | Optimal testing of VLSI analog circuits Chieh-Yuan Chao, Hung-Jen Lin, L. Miler · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1997 | 52 |
| 49 | Room reverberation effects in hearing aid feedback cancellation James Mitchell Kates · The Journal of the Acoustical Society of America | 2001 | 52 |
| 50 | A layout-based approach for ordering scan chain flip-flops Samy Makar | 27 Nov 2002 | 51 |
Citations are OpenAlex's own counts, from its 2026-09-23 snapshot, so the ranking can differ from Google Scholar or Web of Science. A paper is listed for an institution when any of its authors gave it as an affiliation; retracted papers and papers whose citation count cannot be traced to citing works are left out, and a preprint and the article it became are shown once. Release dates are OpenAlex's: where a source gave only a month or a year, that is what is shown. How the lists are chosen.