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Institution · Rambus (United States)

Most cited papers from Rambus (United States)

Rambus (United States)

What are the most cited papers from Rambus (United States)?

The most cited paper from Rambus (United States) is "Frequency-independent equivalent-circuit model for on-chip spiral inductors" (Yu Kevin Cao, Robert A. Groves, Xuejue Huang et al., 2003), with 378 citations. Next come "A semidigital dual delay-locked loop" (337) and "Understanding the Energy Consumption of Dynamic Random Access Memories" (260).

Showing 50 of 60 papers. Every paper with more than 44 citations is listed.

Most cited papers, sortable by citations and release date
#Paper
1 Frequency-independent equivalent-circuit model for on-chip spiral inductors Yu Kevin Cao, Robert A. Groves, Xuejue Huang et al. · IEEE Journal of Solid-State Circuits Mar 2003 378
2 A semidigital dual delay-locked loop Stefanos Sidiropoulos, Mark Horowitz · IEEE Journal of Solid-State Circuits 1997 337
3 Understanding the Energy Consumption of Dynamic Random Access Memories Thomas Vogelsang Conference paper Dec 2010 260
4 Meltdown Moritz Lipp, Michael Schwarz, Daniel Gruss et al. · Communications of the ACM 21 May 2020 241
5 A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS John W. Poulton, Robert Alan Palmer, Andrew M. Fuller et al. · IEEE Journal of Solid-State Circuits 29 Nov 2007 239
6 Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell Jared L. Zerbe, Carl W. Werner, Vladimir Marko Stojanovic et al. · IEEE Journal of Solid-State Circuits Dec 2003 228
7 Accumulate-Repeat-Accumulate Codes Aliazam Abbasfar, D. Divsalar, Kung Yao · IEEE Transactions on Communications Apr 2007 195
8 A portable digital DLL for high-speed CMOS interface circuits Bruno W. Garlepp, Kevin Donnelly, Jun Kim et al. · IEEE Journal of Solid-State Circuits May 1999 187
9 Empathetic Leadership: How Leader Emotional Support and Understanding Influences Follower Performance Ned Kock, Milton Ray Mayfield, Jacqueline Rowley Mayfield et al. · Journal of Leadership & Organizational Studies 17 Oct 2018 183
10 A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM T.H. Lee, Kevin Donnelly, J.T.C. Ho et al. · IEEE Journal of Solid-State Circuits 1994 178
11 Modeling and analysis of high-speed links Vladimir Marko Stojanovic, Mark Horowitz Conference paper 3 Feb 2004 176
12 Elligator Daniel J. Bernstein, Mike Hamburg, Anna Krasnova et al. Conference paperOpen access 2013 165
13 A 155-MHz clock recovery delay- and phase-locked loop T.H. Lee, John F. Bulzacchelli · IEEE Journal of Solid-State Circuits 1992 162
14 Circuits and techniques for high-resolution measurement of on-chip power supply noise E. Alon, Vladimir Marko Stojanovic, Mark Horowitz · IEEE Journal of Solid-State Circuits Apr 2005 160
15 Autonomous dual-mode (PAM2/4) serial link transceiver with adaptive equalization and data recovery Vladimir Marko Stojanovic, A. Ho, Bruno W. Garlepp et al. · IEEE Journal of Solid-State Circuits Apr 2005 150
16 SoC It to EM: ElectroMagnetic Side-Channel Attacks on a Complex System-on-Chip John M. Longo, Erik Mulder, Daniel Page et al. · Lecture notes in computer science Conference paperOpen access 2015 146
17 Adaptive bandwidth DLLs and PLLs using regulated supply CMOS buffers Stefanos Sidiropoulos, Dean Liu, Jaeha Kim et al. Conference paper 7 Nov 2002 143
18 Simulation and Analysis of Random Decision Errors in Clocked Comparators Jong-Wook Kim, Brian S. Leibowitz, Jin Ren et al. · IEEE Transactions on Circuits and Systems I Regular Papers 30 Jul 2009 140
19 Replica Compensated Linear Regulators for Supply-Regulated Phase-Locked Loops E. Alon, Junyeop Kim, Sudhakar Pamarti et al. · IEEE Journal of Solid-State Circuits 31 Jan 2006 138
20 Mid-fidelity approach to aerodynamic simulations of unconventional VTOL aircraft configurations Matteo Tugnoli, D. Montagnani, Monica Syal et al. · Aerospace Science and Technology Open access 12 May 2021 136
21 A variable-frequency parallel I/O interface with adaptive power-supply regulation Gu-Yeon Wei, Jong-Wook Kim, D. Liu et al. · IEEE Journal of Solid-State Circuits Nov 2000 121
22 A 2.5 nJ/bit 0.65 V Pulsed UWB Receiver in 90 nm CMOS Fred S. Lee, Anantha P. Chandrakasan · IEEE Journal of Solid-State Circuits 29 Nov 2007 119
23 Resistive Random Access Memory for Future Information Processing System Huaqiang Wu, Xiao Hu Wang, Bin Gao et al. · Proceedings of the IEEE 2 May 2017 117
24 Direct RAMbus technology: the new main memory standard Richard Crisp · IEEE Micro 1997 112
25 Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse Jinwoo Kim, Gauthaman Murali, Heechun Park et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 Aug 2020 105
26 Reduction of pump current mismatch in charge-pump PLL MinHo Hwang, Jong-Wook Kim, Deog‐Kyoon Jeong · Electronics Letters 28 Jan 2009 105
27 10-Gbps, 5.3-mW Optical Transmitter and Receiver Circuits in 40-nm CMOS Frankie Y. Liu, Dinesh D. Patil, Jon K. Lexau et al. · IEEE Journal of Solid-State Circuits 5 Jun 2012 100
28 Tighter Proofs of CCA Security in the Quantum Random Oracle Model Nina Bindel, Mike Hamburg, Kathrin Hövelmanns et al. · Lecture notes in computer science Conference paper 2019 94
29 A 0.4-4-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs Kuo‐Cheng Chang, Jason Wei, Ching-Chao Huang et al. · IEEE Journal of Solid-State Circuits May 2003 91
30 A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology Reza Navid, E-Hung Chen, Masum Hossain et al. · IEEE Journal of Solid-State Circuits 19 Dec 2014 86
31 Multiple Edge Responses for Fast and Accurate System Simulations Jihong Ren, Kyung Suk Oh · IEEE Transactions on Advanced Packaging Nov 2008 85
32 A 4.3 GB/s Mobile Memory Interface With Power-Efficient Bandwidth Scaling Brian S. Leibowitz, Robert Alan Palmer, John W. Poulton et al. · IEEE Journal of Solid-State Circuits 24 Mar 2010 83
33 Power-efficient metastability error reduction in CMOS flash A/D converters C.L. Portmann, T.H. Meng · IEEE Journal of Solid-State Circuits 1996 73
34 Rethinking DRAM Power Modes for Energy Proportionality Krishna T. Malladi, Ian Shaeffer, Liji Gopalakrishnan et al. Conference paper Dec 2012 69
35 Chosen Ciphertext k-Trace Attacks on Masked CCA2 Secure Kyber Mike Hamburg, Julius Hermelink, Robert Primas et al. · IACR Transactions on Cryptographic Hardware and Embedded Systems Open access 11 Aug 2021 68
36 Ultralow Power 80 Gb/s Arrayed CMOS Silicon Photonic Transceivers for WDM Optical Links Xuezhe Zheng, Frankie Liu, Jon K. Lexau et al. · Journal of Lightwave Technology 15 Dec 2011 68
37 A 14mW 6.25Gb/s Transceiver in 90nm CMOS for Serial Chip-to-Chip Communications Robert Alan Palmer, John W. Poulton, William J. Dally et al. Conference paper Feb 2007 66
38 A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface Haechang Lee, Kun-Yung Ken Chang, Jung‐Hoon Chun et al. · IEEE Journal of Solid-State Circuits 24 Mar 2009 60
39 Adaptive equalization and data recovery in a dual-mode (PAM2/4) serial link transceiver Vladimir Marko Stojanovic, A. Ho, Bruno W. Garlepp et al. Conference paper 26 Oct 2004 60
40 Improving Power and Data Efficiency with Threaded Memory Modules Frederick A. Ware, Craig Hampel · Proceedings, IEEE International Conference on Computer Design/Proceedings - IEEE International Conference on Computer Design Conference paper Oct 2006 60
41 Accurate Characterization of Broadband Multiconductor Transmission Lines for High-Speed Digital Systems Joong-Ho Kim, Dan Kyung Suk Oh, Woopoung Kim · IEEE Transactions on Advanced Packaging Nov 2010 59
42 Clocking and circuit design for a parallel I/O on a first-generation CELL processor Ken Chang, Sudhakar Pamarti, Kambiz Kaviani et al. Conference paper 30 Aug 2005 59
43 High-frequency noise in nanoscale metal oxide semiconductor field effect transistors Reza Navid, Christoph Jungemann, Thomas H. Lee et al. · Journal of Applied Physics 15 Jun 2007 57
44 An 11-million Transistor Neural Network Execution Engine M.M. Griffin, G. Tahara, Kurt Knorpp et al. Conference paper 1991 56
45 A 2 Gb/s/pin 4-PAM parallel bus interface with transmit crosstalk cancellation, equalization, and integrating receivers Jared L. Zerbe, Pak Shing Chau, Carl W. Werner et al. Conference paper 13 Nov 2002 56
46 HfO 2 /Al 2 O 3 multilayer for RRAM arrays: a technique to improve tail-bit retention Xueyao Huang, Huaqiang Wu, Bin Gao et al. · Nanotechnology 18 Aug 2016 55
47 Relaxation Effect in RRAM Arrays: Demonstration and Characteristics Chen Wang, Huaqiang Wu, Bin Gao et al. · IEEE Electron Device Letters 11 Dec 2015 53
48 Investigating the Impact of Supply Noise on the Jitter in Gigabit I/O Interfaces Ralf Schmitt, Hai Yan Lan, Chris Madden et al. Conference paper Oct 2007 53
49 A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR Brian S. Leibowitz, Jade Kizer, Haechang Lee et al. Conference paper Feb 2007 53
50 Power Optimized ADC-Based Serial Link Receiver E-Hung Chen, Ramy Yousry, Chih-Kong Ken Yang · IEEE Journal of Solid-State Circuits 15 Feb 2012 53

Citations are OpenAlex's own counts, from its 2026-09-23 snapshot, so the ranking can differ from Google Scholar or Web of Science. A paper is listed for an institution when any of its authors gave it as an affiliation; retracted papers and papers whose citation count cannot be traced to citing works are left out, and a preprint and the article it became are shown once. Release dates are OpenAlex's: where a source gave only a month or a year, that is what is shown. How the lists are chosen.