Institution · Faraday Technology (Taiwan)
Most cited papers from Faraday Technology (Taiwan)
What are the most cited papers from Faraday Technology (Taiwan)?
The most cited paper from Faraday Technology (Taiwan) is "A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing" (Ming-Hsien Tu, Jihi-Yu Lin, Ming-Chien Tsai et al., 2012), with 173 citations. Next come "Structured ASIC, evolution or revolution?" (78) and "Statistical diagnosis for intermittent scan chain hold-time fault" (74).
Showing 50 of 60 papers. Every paper with more than 6 citations is listed.
| # | Paper | ||
|---|---|---|---|
| 1 | A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing Ming-Hsien Tu, Jihi-Yu Lin, Ming-Chien Tsai et al. · IEEE Journal of Solid-State Circuits | 13 Apr 2012 | 173 |
| 2 | Structured ASIC, evolution or revolution? Kun-cheng Wu, Yu-Wen Tsai | 18 Apr 2004 | 78 |
| 3 | Statistical diagnosis for intermittent scan chain hold-time fault Yu Huang, Wu-Tung Cheng, Sudhakar M. Reddy et al. | 8 Jul 2004 | 74 |
| 4 | A built-in self-test and self-diagnosis scheme for embedded SRAM Chih-Wea Wang, Chi-Feng Wu, Jin-Fu Li et al. | 8 Nov 2002 | 62 |
| 5 | A High-Definition H.264/AVC Intra-Frame Codec IP for Digital Video and Still Camera Applications Chen‐Wei Ku, Chang-Hsin Cheng, Gong-San Yu et al. · IEEE Transactions on Circuits and Systems for Video Technology | Aug 2006 | 58 |
| 6 | Post-placement power optimization with multi-bit flip-flops Yao-Tsung Chang, Chih‐Cheng Hsu, Mark Po-Hung Lin et al. | Nov 2010 | 56 |
| 7 | A High Linearity, Fast-Locking Pulsewidth Control Loop With Digitally Programmable Duty Cycle Correction for Wide Range Operation Kuo‐Hsing Cheng, Chia-Wei Su, Kai-Fei Chang · IEEE Journal of Solid-State Circuits | 2008 | 56 |
| 8 | ReBISR: A Reconfigurable Built-In Self-Repair Scheme for Random Access Memories in SOCs Tsu-Wei Tseng, Jin-Fu Li, Chih‐Chiang Hsu · IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 3 Nov 2009 | 52 |
| 9 | Fast Fixed-Outline 3-D IC Floorplanning With TSV Co-Placement Cha-Ru Li, Wai-Kei Mak, Ting-Chi Wang · IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 11 Apr 2012 | 49 |
| 10 | An AND-Type Match-Line Scheme for High-Performance Energy-Efficient Content Addressable Memories Hanxiu Li, Chun-Chi Chen, Jingsong Wang et al. · IEEE Journal of Solid-State Circuits | 28 Apr 2006 | 47 |
| 11 | A 5-Gb/s Inductorless CMOS Adaptive Equalizer for PCI Express Generation II Applications Kuo‐Hsing Cheng, Yu-Chang Tsai, Yen-Hsueh Wu et al. · IEEE Transactions on Circuits & Systems II Express Briefs | May 2010 | 42 |
| 12 | A CMOS 8-Bit 1.6-GS/s DAC With Digital Random Return-to-Zero Wei-Hsin Tseng, Jieh-Tsorng Wu, Yung-Cheng Chu · IEEE Transactions on Circuits & Systems II Express Briefs | 22 Dec 2010 | 41 |
| 13 | A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist Nan-Chun Lien, Li-Wei Chu, Chien-Hen Chen et al. · IEEE Transactions on Circuits and Systems I Regular Papers | 8 Sep 2014 | 39 |
| 14 | A Reconfigurable Built-In Self-Repair Scheme for Multiple Repairable RAMs in SOCs Tsu-Wei Tseng, Jin-Fu Li, Chih‐Chiang Hsu et al. · Proceedings/Proceedings - International Test Conference | Oct 2006 | 35 |
| 15 | Value assignment of Adjustable Delay Buffers for clock skew minimization in multi-voltage mode designs Yu-Shih Su, Wing-Kai Hon, Cheng-Chih Yang et al. | 2 Nov 2009 | 35 |
| 16 | A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist Chien-Yu Lu, Ching-Te Kent Chuang, Shyh-Jye Jerry Jou et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 8 May 2014 | 35 |
| 17 | Design theory and implementation for low-power segmented bus systems Wen B. Jone, J. S. Wang, Hsueh-I Lu et al. · ACM Transactions on Design Automation of Electronic Systems | 2003 | 35 |
| 18 | Mining interesting association rules from customer databases and transaction databases Pauray S. M. Tsai, Chien‐Ming Chen · Information Systems | 16 Jul 2003 | 34 |
| 19 | Efficient diagnosis for multiple intermittent scan chain hold-time faults Yu Huang, Huan-Yung Tseng, Wu-Tung Cheng et al. | 2003 | 33 |
| 20 | Clock Skew Minimization in Multi-Voltage Mode Designs Using Adjustable Delay Buffers Yu-Shih Su, Wing-Kai Hon, Cheng-Chih Yang et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 30 Nov 2010 | 32 |
| 21 | Low switching noise and load-adaptive output buffer design techniques Shyh-Jye Jerry Jou, Shu-Hua Kuo, Jui-Ta Chiu et al. · IEEE Journal of Solid-State Circuits | 2001 | 32 |
| 22 | INTEGRA Iris Hui-Ru Jiang, Chih-Long Chang, Yuming Yang et al. | 22 Mar 2011 | 27 |
| 23 | Overview on electrostatic discharge protection designs for mixed-voltage I/O interfaces: design concept and circuit implementations Ming-Dou Ker, Kai Lin · IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications | Feb 2006 | 26 |
| 24 | A Built-In Self-Repair Scheme for Multiport RAMs Tsu-Wei Tseng, Chung‐Hsien Wu, Yu-Jen Huang et al. | May 2007 | 26 |
| 25 | Simultaneous Optimization of Analog Circuits With Reliability and Variability for Applications on Flexible Electronics Yen‐Lung Chen, Wan-Rong Wu, Chien‐Nan Jimmy Liu et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2014 | 25 |
| 26 | A 0.5-V 28-nm 256-kb Mini-Array Based 6T SRAM With Vtrip-Tracking Write-Assist Shang-Lin Wu, Kuang-Yu Li, Po-Tsang Huang et al. · IEEE Transactions on Circuits and Systems I Regular Papers | 24 Mar 2017 | 24 |
| 27 | A mm-wave CMOS multimode frequency divider Hsien‐Ku Chen, Hsien-Jui Chen, Da‐Chiang Chang et al. | Feb 2009 | 24 |
| 28 | Electrostatic discharge protection design for mixed-voltage CMOS I/O buffers Ming‐Dou Ker, Chien-Hui Chuang · IEEE Journal of Solid-State Circuits | Aug 2002 | 24 |
| 29 | A 0.6 V, 4.32 mW, 68 GHz Low Phase-Noise VCO With Intrinsic-Tuned Technique in 0.13 $\mu$m CMOS Hsien‐Ku Chen, Hsien-Jui Chen, Da‐Chiang Chang et al. · IEEE Microwave and Wireless Components Letters | 24 Jun 2008 | 22 |
| 30 | NEMO: A New Implicit-Connection-Graph-Based Gridless Router With Multilayer Planes and Pseudo Tile Propagation Yong Li, Hsin-Yu Chen, Chih-Ta Lin · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 28 Mar 2007 | 22 |
| 31 | Intermittent scan chain fault diagnosis based on signal probability analysis Yu Huang, Wu-Tung Cheng, Cheng‐Ju Hsieh et al. | 3 Jun 2004 | 21 |
| 32 | A 5.26-GHz CMOS Up-Conversion Mixer for IEEE 802.11a WLAN Steve Hung‐Lung Tu, Sky Chang-Hung Chen | May 2008 | 19 |
| 33 | A routing algorithm for flip-chip design Jiawei Fang, I-Jye Lin, Ping-Hung Yuh et al. | 22 Dec 2005 | 18 |
| 34 | A Low-Power CMOS Voltage Reference Circuit Based On Subthreshold Operation Chia-Wei Chang, Tien-Yu Lo, Chia-Min Chen et al. | May 2007 | 18 |
| 35 | On-Chip ESD Protection Design With Substrate-Triggered Technique for Mixed-Voltage I/O Circuits in Subquarter-Micrometer CMOS Process Ming‐Dou Ker, Kai Lin, C.-H. Chuang · IEEE Transactions on Electron Devices | 28 Sep 2004 | 17 |
| 36 | A 55nm 0.55v 6T SRAM with variation-tolerant dual-tracking word-line under-drive and data-aware write-assist Yi-Wei Lin, Hao-I Yang, Geng-Cing Lin et al. | 30 Jul 2012 | 16 |
| 37 | A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM Chih-Wea Wang, Chi-Feng Wu, Jin-Fu Li et al. · Journal of Electronic Testing | Dec 2002 | 16 |
| 38 | On the design of power-rail esd clamp circuit with consideration of gate leakage current in 65-nm low-voltage CMOS process Ming‐Dou Ker, Po-Yen Chiu, Fu-Yi Tsai et al. | May 2009 | 14 |
| 39 | A Hierarchical Test Scheme for System-On-Chip Designs Jin-Fu Li, Hsin-Jung Huang, Jeng-Bin Chen et al. | 4 Mar 2002 | 13 |
| 40 | A 0.33-V, 500-kHz, 3.94-$\mu\hbox{W}$ 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist Chien-Yu Lu, Ming-Hsien Tu, Hwai‐I Yang et al. · IEEE Transactions on Circuits & Systems II Express Briefs | Dec 2012 | 13 |
| 41 | A low power and fast wake up circuit Hung-Wei Chen, Wen-Cheng Yen | 4 Oct 2004 | 13 |
| 42 | Ultra-low-leakage power-rail ESD clamp circuit in nanoscale low-voltage CMOS process Po-Yen Chiu, Ming‐Dou Ker, Fu-Yi Tsai et al. · IEEE International Reliability Physics Symposium proceedings | Apr 2009 | 12 |
| 43 | ESD protection design for I/O cells with embedded SCR structure as power-rail ESD clamp device in nanoscale CMOS technology Ming‐Dou Ker, Kai Lin · IEEE Journal of Solid-State Circuits | 24 Oct 2005 | 12 |
| 44 | 0.339fJ/bit/search energy-efficient TCAM macro design in 40nm LP CMOS Po-Tsang Huang, Shu-Lin Lai, Ching-Te Chuang et al. | Nov 2014 | 11 |
| 45 | An Efficient Graph-Based Algorithm for ESD Current Path Analysis Chih-Hung Liu, Hsin‐Yun Liu, C.‐W. Lin et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 24 Jul 2008 | 10 |
| 46 | Test cycle power optimization for scan-based designs Kun-Han Hans Tsai, Yu Huang, Wu-Tung Cheng et al. | Nov 2010 | 10 |
| 47 | Towards Process Variation-Aware Power Gating Chingwei Yeh, Yuanchang Chen, Jinn‐Shyan Wang · IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 25 Oct 2011 | 10 |
| 48 | Beat the competition P.H. Chen · IEEE Circuits and Devices Magazine | May 2004 | 10 |
| 49 | Keeping Deep Lithography Simulators Updated: Global–Local Shape-Based Novelty Detection and Active Learning Hao-Chiang Shao, Hsing-Lei Ping, Kuo-Shiuan Chen et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 18 Jul 2022 | 9 |
| 50 | A Systematic Design Approach to the Band-Tracking Packet Detector in OFDM-Based Ultrawideband Systems Jyh-Ting Lai, An-Yeu Andy Wu, Wen-Chiang Chen · IEEE Transactions on Vehicular Technology | Nov 2007 | 9 |
Citations are OpenAlex's own counts, from its 2026-09-23 snapshot, so the ranking can differ from Google Scholar or Web of Science. A paper is listed for an institution when any of its authors gave it as an affiliation; retracted papers and papers whose citation count cannot be traced to citing works are left out, and a preprint and the article it became are shown once. Release dates are OpenAlex's: where a source gave only a month or a year, that is what is shown. How the lists are chosen.