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Most cited papers from Mentor Technologies

Mentor Technologies

What are the most cited papers from Mentor Technologies?

The most cited paper from Mentor Technologies is "Embedded Deterministic Test" (Janusz Rajski, Jerzy Tyszer, Mark Kassab et al., 2004), with 529 citations. Next come "Carbon Nanomaterials for Next-Generation Interconnects and Passives: Physics, Status, and Prospects" (443) and "OASYS: a framework for analog circuit synthesis" (436).

Showing 50 of 59 papers. Every paper with more than 74 citations is listed.

Most cited papers, sortable by citations and release date
#Paper
1 Embedded Deterministic Test Janusz Rajski, Jerzy Tyszer, Mark Kassab et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems May 2004 529
2 Carbon Nanomaterials for Next-Generation Interconnects and Passives: Physics, Status, and Prospects Hong Li, Chuan Xu, Navin Srivastava et al. · IEEE Transactions on Electron Devices 24 Aug 2009 443
3 OASYS: a framework for analog circuit synthesis Ramesh Harjani, Rob A. Rutenbar, Larry Richard Carley · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 1989 436
4 Markov random field models for unsupervised segmentation of textured color images D. Panjwani, Glenn E. Healey · IEEE Transactions on Pattern Analysis and Machine Intelligence 1995 421
5 Built-in test for circuits with scan based on reseeding of multiple-polynomial linear feedback shift registers Sybille Hellebrand, Janusz Rajski, Steffen Tarnick et al. · IEEE Transactions on Computers 1995 409
6 Embedded deterministic test for low cost manufacturing test Janusz Rajski, Jerzy Tyszer, Mark Kassab et al. Conference paper 25 Jun 2003 404
7 An O-tree representation of non-slicing floorplan and its applications Pei-Ning Guo, Chung‐Kuan Cheng, Takeshi Yoshimura Conference paper Jun 1999 384
8 Data Structures for Mobile Data Julien Basch, Leonidas Guibas, John E. Hershberger 1997 350
9 VHDL-AMS-a hardware description language for analog and mixed-signal applications E. Christen, Kenneth Bakalar · IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing 1999 289
10 Logic BIST for large industrial designs: real issues and case studies G. Hetherington, T. Fryars, Nagesh Tamarapalli et al. Conference paper 20 Jan 2003 284
11 Vickrey prices and shortest paths: what is an edge worth? John E. Hershberger, Subhash Suri Conference paper 2001 239
12 Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs Santiago Remersaro, Xijiang Lin, Zhuo Zhang et al. · Proceedings/Proceedings - International Test Conference Conference paper Oct 2006 239
13 HAM: a general purpose hypertext abstract machine Bradford Campbell, M. Goodman Joseph · Communications of the ACM Open access Jul 1988 239
14 Computing minimum length paths of a given homotopy class John E. Hershberger, Jack Scott Snoeyink · Computational Geometry Open access Jun 1994 226
15 Cell-Aware Test Friedrich Hapke, W. Redemund, Andreas Glowatz et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Open access 18 Aug 2014 201
16 Finding the k shortest simple paths John E. Hershberger, Matthew Maxel, Subhash Suri · ACM Transactions on Algorithms Nov 2007 189
17 On the Applicability of Single-Walled Carbon Nanotubes as VLSI Interconnects N. Srivastava, Hong Li, Franz Kreupl et al. · IEEE Transactions on Nanotechnology 30 Jan 2009 181
18 Optimal core wrapper width selection and SOC test scheduling based on 3-D bin packing algorithm Yu Huang, Sudhakar M. Reddy, Wu-Tung Cheng et al. Conference paper 25 Jun 2003 164
19 Impact of multiple-detect test patterns on product quality Brady Benware, Chris Schuermyer, Nagesh Tamarapalli et al. Conference paper 8 Jul 2004 159
20 ISPD 2015 Benchmarks with Fence Regions and Routing Blockages for Detailed-Routing-Driven Placement Ismail S. K. Bustany, David Chinnery, Joseph R. Shinnerl et al. Conference paper 12 Mar 2015 154
21 Triangulating Topological Spaces Herbert Edelsbrunner, Nimish R. Shah · International Journal of Computational Geometry & Applications Aug 1997 148
22 Resource allocation and test scheduling for concurrent test of core-based SOC design Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai et al. Conference paper 14 Nov 2002 146
23 Convolutional compaction of test responses Janusz Rajski, Jerzy Tyszer, Chen Wang et al. Conference paper 8 Jul 2004 140
24 Constructive multi-phase test point insertion for scan-based BIST Nagesh Tamarapalli, Janusz Rajski Conference paper 23 Dec 2002 139
25 Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects Xijiang Lin, Kun-Han Hans Tsai, Chen Wang et al. · Proceedings - Asian Test Symposium/Proceedings Conference paper Nov 2006 135
26 An efficient logic emulation system J. N. Varghese, M. Butts, J. Batcheller · IEEE Transactions on Very Large Scale Integration (VLSI) Systems Jun 1993 127
27 Physics-based Electromigration Assessment for Power Grid Networks Xin Huang, Tan Yu, Valeriy Sukharev et al. Conference paper 27 May 2014 126
28 Nonlinear transformer model for circuit simulation J.H.K. Chan, Andrei Vladimirescu, Xiaohui Gao et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Apr 1991 126
29 Fast pixel-based mask optimization for inverse lithography Yuri Granik · Journal of Micro/Nanolithography MEMS and MOEMS Oct 2006 120
30 ICCAD-2012 CAD contest in fuzzy pattern matching for physical verification and benchmark suite J. Andres Torres Conference paper 5 Nov 2012 119
31 Ring Generators—New Devices for Embedded Test Applications Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 31 Aug 2004 118
32 ENOR Bernard N. Sheehan Conference paper Jun 1999 118
33 Resolution enhancement technology: the past, the present, and extensions for the future Franklin M. Schellenberg · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE Conference paper 28 May 2004 116
34 On computing the sizes of detected delay faults V. Iyengar, Barry K. Rosen, John A. Waicukauski · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Mar 1990 115
35 Trends in functional verification Harry D. Foster Conference paper 2 Jun 2015 113
36 Power Grid Electromigration Checking Using Physics-Based Models Sandeep Chatterjee, Valeriy Sukharev, Farid N. Najm · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 9 Feb 2017 106
37 SOC test scheduling using simulated annealing Wei Zou, Sudhakar M. Reddy, Irith Pomeranz et al. Conference paper 31 Oct 2003 101
38 Thermal Measurement and Modeling of Multi-Die Packages A. Poppe, Yan Zhang, John P. Wilson et al. · IEEE Transactions on Components and Packaging Technologies Open access 26 Feb 2009 96
39 Deformable Free-Space Tilings for Kinetic Collision Detection† Pankaj K. Agarwal, Julien Basch, Leonidas Guibas et al. · The International Journal of Robotics Research Mar 2002 94
40 Test data decompression for multiple scan designs with boundary scan Janusz Rajski, Jerzy Tyszer, N. Zacharia · IEEE Transactions on Computers 1998 93
41 Physics-Based Electromigration Models and Full-Chip Assessment for Power Grid Networks Xin Huang, Armen Kteyan, Sheldon X.-D. Tan et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 5 Feb 2016 89
42 Survey of Scan Chain Diagnosis Yu Huang, Ruifeng Guo, Wu-Tung Cheng et al. · IEEE Design & Test of Computers May 2008 89
43 Analyzing Volume Diagnosis Results with Statistical Learning for Yield Improvement Huaxing Tang, Manish Sharma, Janusz Rajski et al. · Proceedings/Proceedings - European Test Workshop Conference paper May 2007 88
44 Automated synthesis of phase shifters for built-in self-test applications Janusz Rajski, Nagesh Tamarapalli, Jerzy Tyszer · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2000 85
45 Decompression of test data using variable-length seed LFSRs N. Zacharia, Janusz Rajski, Jerzy Tyszer Conference paper 19 Nov 2002 83
46 Floorplanning using a tree representation Pei-Ning Guo, T. Takahashi, Chung-Kuan Cheng et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Open access 2001 83
47 On the Complexity of Time-Dependent Shortest Paths Luca Foschini, John E. Hershberger, Subhash Suri · Algorithmica 17 Nov 2012 81
48 Finite memory test response compactors for embedded test applications Janusz Rajski, Jerzy Tyszer, Chen Wang et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Apr 2005 81
49 High Performance Lithography Hotspot Detection With Successively Refined Pattern Identifications and Machine Learning Duo Ding, J. Andres Torres, David Zhigang Pan · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 18 Oct 2011 81
50 At-speed scan test with low switching activity Elham Moghaddam, Janusz Rajski, Mark Kassab et al. Conference paper Apr 2010 80

Citations are OpenAlex's own counts, from its 2026-09-23 snapshot, so the ranking can differ from Google Scholar or Web of Science. A paper is listed for an institution when any of its authors gave it as an affiliation; retracted papers and papers whose citation count cannot be traced to citing works are left out, and a preprint and the article it became are shown once. Release dates are OpenAlex's: where a source gave only a month or a year, that is what is shown. How the lists are chosen.