Most cited papers in 3D IC and TSV technologies
What are the most cited papers in 3D IC and TSV technologies?
The most cited paper in 3D IC and TSV technologies is "Fracture Toughness Determinations by Indentation" (Anthony Glyn Evans, E.A. Charles, 1976), with 2,344 citations. Next come "Lead-free Solders in Microelectronics" (1,970) and "The future of wires" (1,441).
Showing 50 of 100 papers. Every paper with more than 301 citations is listed.
| # | Paper | ||
|---|---|---|---|
| 1 | Fracture Toughness Determinations by Indentation Anthony Glyn Evans, E.A. Charles · Journal of the American Ceramic Society | Jul 1976 | 2,344 |
| 2 | Lead-free Solders in Microelectronics Mulugeta Abtew, Guna S Selvaduray · Materials Science and Engineering R Reports | Jun 2000 | 1,970 |
| 3 | The future of wires R. Ho, Ken Mai, Mark Horowitz · Proceedings of the IEEE | Apr 2001 | 1,441 |
| 4 | Six cases of reliability study of Pb-free solder joints in electronic packaging technology Ke Zeng, K. N. Tu · Materials Science and Engineering R Reports | Jun 2002 | 1,367 |
| 5 | Equivalent Circuit Models for Three-Dimensional Multiconductor Systems Albert E. Ruehli · IEEE Transactions on Microwave Theory and Techniques | Mar 1974 | 1,269 |
| 6 | Damascene copper electroplating for chip interconnections Panayotis C. Andricacos, Cyprian E. Uzoh, John O. Dukovic et al. · IBM Journal of Research and Development | Sep 1998 | 1,226 |
| 7 | HotSpot: a compact thermal modeling methodology for early-stage VLSI design Wei Huang, Sudeep Ghosh, S. Velusamy et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems | May 2006 | 1,116 |
| 8 | 3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration Kaustav Banerjee, Shukri J. Souri, Pawan Kapur et al. · Proceedings of the IEEE | May 2001 | 1,030 |
| 9 | Silicon on insulator material technology MICHEL BRUEL · Electronics Letters | 6 Jul 1995 | 1,015 |
| 10 | Demystifying 3D ICs: The Pros and Cons of Going Vertical William Rhett Davis, John Wilson, Stephen E. Mick et al. · IEEE Design & Test of Computers | Jun 2005 | 841 |
| 11 | Ceramic and Glass‐Ceramic Packaging in the 1990s Rao Tummala · Journal of the American Ceramic Society | May 1991 | 743 |
| 12 | Nanomoulding with amorphous metals Golden Kumar, Hong X. Tang, Jan Schroers · Nature | Feb 2009 | 718 |
| 13 | Recent advances of conductive adhesives as a lead-free alternative in electronic packaging: Materials, processing, reliability and applications Yi Li, Ching Ping Wong · Materials Science and Engineering R Reports | 2006 | 715 |
| 14 | Three-dimensional integrated circuits Anna W. Topol, Douglas Charles La Tulipe, L. Shi et al. · IBM Journal of Research and Development | Jul 2006 | 706 |
| 15 | Recent Advances and Trends in Advanced Packaging John Hon-Shing Lau · IEEE Transactions on Components Packaging and Manufacturing Technology | 18 Jan 2022 | 694 |
| 16 | Wire routing by optimizing channel assignment within large apertures Akihiro Hashimoto, James D. Stevens | 1971 | 682 |
| 17 | Reliability challenges in 3D IC packaging technology K. N. Tu · Microelectronics Reliability | 26 Oct 2010 | 657 |
| 18 | Lithography gets extreme Christian C. Wagner, Noreen Harned · Nature Photonics | 23 Dec 2009 | 641 |
| 19 | Computer-aided design of analog and mixed-signal integrated circuits Georges E. Gielen, Rob A. Rutenbar · Proceedings of the IEEE | Dec 2000 | 616 |
| 20 | Die Stacking (3D) Microarchitecture Bryan Black, Daniel Pantuso, Paul A. Reed et al. | Dec 2006 | 607 |
| 21 | Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs Robert Patti · Proceedings of the IEEE | Jun 2006 | 604 |
| 22 | SEMICONDUCTOR WAFER BONDING U. Gösele, Qiaoling Tong · Annual Review of Materials Science | Aug 1998 | 598 |
| 23 | Electrical Modeling and Characterization of Through Silicon via for Three-Dimensional ICs Guruprasad Katti, Michele Stucchi, Kristin De Meyer et al. · IEEE Transactions on Electron Devices | Dec 2009 | 591 |
| 24 | Measurement and Interpretation of stress in aluminum-based metallization as a function of thermal history P. A. Flinn, Donald S. Gardner, William D. Nix · IEEE Transactions on Electron Devices | Mar 1987 | 591 |
| 25 | Wafer bonding for silicon-on-insulator technologies J. B. Lasky · Applied Physics Letters | 6 Jan 1986 | 578 |
| 26 | Interconnect scaling-the real limiter to high performance ULSI Mark T. Bohr | 19 Nov 2002 | 552 |
| 27 | Microelectronics Packaging Handbook Rao Tummala, Eugene J. Rymaszewski, Y. C. Lee · Journal of Electronic Packaging | Sep 1989 | 535 |
| 28 | The TimberWolf placement and routing package Carl Sechen, Alberto L. Sangiovanni-Vincentelli · IEEE Journal of Solid-State Circuits | Apr 1985 | 534 |
| 29 | A review of lead-free solders for electronics applications Shunfeng Cheng, Chien‐Ming Huang, MICHAEL G. PECHT · Microelectronics Reliability | Jul 2017 | 529 |
| 30 | Interconnect limits on gigascale integration (GSI) in the 21st century Jeffrey A. Davis, R. Venkatesan, Alex E. Kaloyeros et al. · Proceedings of the IEEE | Mar 2001 | 516 |
| 31 | Silicon-to-silicon direct bonding method Masaru Shimbo, K. Furukawa, Kota Fukuda et al. · Journal of Applied Physics | 15 Oct 1986 | 513 |
| 32 | A Procedure for Placement of Standard-Cell VLSI Circuits A.E. Dunlop, Brian W. Kernighan · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1985 | 507 |
| 33 | Kinetic analysis of the soldering reaction between eutectic SnPb alloy and Cu accompanied by ripening H. K. Kim, K. N. Tu · Physical review. B, Condensed matter | 15 Jun 1996 | 506 |
| 34 | High-Frequency Scalable Electrical Model and Analysis of a Through Silicon Via (TSV) Joohee Kim, Jun So Pak, Jonghyun Cho et al. · IEEE Transactions on Components Packaging and Manufacturing Technology | Feb 2011 | 503 |
| 35 | Three-dimensional silicon integration John U. Knickerbocker, Paul S. Andry, B. Dang et al. · IBM Journal of Research and Development | Nov 2008 | 501 |
| 36 | Electronics Without Lead Yi Li, Kyoung‐sik Moon, Ching Ping Wong · Science | 2 Jun 2005 | 497 |
| 37 | Mechanical stability and adhesion of microstructures under capillary forces. I. Basic theory Carlos H. Mastrangelo, C.H. Hsu · Journal of Microelectromechanical Systems | Mar 1993 | 491 |
| 38 | 8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology Uksong Kang et al. · IEEE Journal of Solid-State Circuits | 2010 | 488 |
| 39 | Through-Silicon Via (TSV) Makoto Motoyoshi · Proceedings of the IEEE | 2009 | 481 |
| 40 | A review: On the development of low melting temperature Pb-free solders Hiren Ramniklal Kotadia, Philip D. Howes, SAMJID H. MANNAN · Microelectronics Reliability | 6 Apr 2014 | 481 |
| 41 | Overview of transient liquid phase and partial transient liquid phase bonding Grant O. Cook, Carl D. Sorensen · Journal of Materials Science | 6 May 2011 | 470 |
| 42 | Adhesive wafer bonding Frank Niklaus, Göran Stemme, Jian‐Qiang Lu et al. · Journal of Applied Physics | Feb 2006 | 469 |
| 43 | Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation Brett Stanley Feero, Partha Pratim Pande · IEEE Transactions on Computers | 19 Aug 2008 | 467 |
| 44 | Simple formulas for two- and three-dimensional capacitances Takeaki Sakurai, Kiichiro Tamaru · IEEE Transactions on Electron Devices | Feb 1983 | 464 |
| 45 | Knights Landing: Second-Generation Intel Xeon Phi Product Avinash Sodani, Roger Gramunt, Jesús Corbal et al. · IEEE Micro | Mar 2016 | 453 |
| 46 | Surface activated bonding of silicon wafers at room temperature Hideki Takagi, Kenya Kikuchi, Ryutaro Maeda et al. · Applied Physics Letters | 15 Apr 1996 | 453 |
| 47 | Hybrid memory cube new DRAM architecture increases density and performance Joe Jeddeloh, Brent Keeth | Jun 2012 | 446 |
| 48 | Kirkendall void formation in eutectic SnPb solder joints on bare Cu and its effect on joint reliability Kejun Zeng, R.J. Stierman, Tz-Cheng Chiu et al. · Journal of Applied Physics | 23 Dec 2004 | 440 |
| 49 | Wafer-to-wafer bonding for microstructure formation Martin A. Schmidt · Proceedings of the IEEE | 1998 | 434 |
| 50 | A thermal-driven floorplanning algorithm for 3D ICs J. Cong, Jie Wei, Yan Zhang | 22 Feb 2005 | 432 |
Citations are OpenAlex's own counts, from its 2026-09-23 snapshot, so the ranking can differ from Google Scholar or Web of Science. A paper is listed for a field when OpenAlex files it under one of the field's topics; retracted papers and papers whose citation count cannot be traced to citing works are left out, and a preprint and the article it became are shown once. Release dates are OpenAlex's: where a source gave only a month or a year, that is what is shown. How the lists are chosen.